Referring to FIG. 1, a block diagram of a data processing system 10 that includes error checking and correction capability according to the prior art is shown. The data processing system 10 includes a central processing unit 11 and a memory unit 12. The central processing unit 11 exchanges signals with apparatus not shown, but which, for example, can include peripheral devices, keyboard signals, etc. The central processing unit 11 applies address signals to the main memory 121 and to the error checking and correction memory 122. The central processing unit 11 also applies data signals to the main memory 121 and the error checking and correction memory 122. The main memory 121, during a read operation, applies signals to a check bit calculation unit 123. The check bit calculation unit 123 and the error checking and correction memory 122 apply signals to the syndrome calculation unit 124. The syndrome calculation unit 124 applies data signals and the syndrome unit 124 applies syndrome signals to the bit correction unit 125.
The operation of the data processing system 10 can be understood as follows. The central processing unit 11, in a write operation of a signal group, generates the error checking and correction signals associated with the signal group to be stored in the main memory 121. The signal group is then stored in the main memory 121 and the error checking and correction signals are stored in the error checking and correction memory 122 at the same address. In a read operation, the addressed signal group in the main memory 121 is applied to the check bit calculator 123 while the associated (i.e., at the same address) error checking and correction signals in the error checking and correction memory 122 are transferred to the syndrome calculation unit 124. The check bit calculation unit 123 provides error checking and correction signals to the syndrome calculation unit 124. Based on a comparison of the signals from the check bit calculation unit 123 and the error checking and correction signals from the error correction code memory, the syndrome calculation unit 124 provides a group of syndrome signals that identifies the correctable bit position in the data signal group. The group of syndrome signals is applied to the bit correction unit 125. In the bit correction unit, the data signal group from the main memory 121 is corrected and transferred to the central processing unit 11.
While the foregoing operation has proven successful for correcting data signal groups stored in a non-volatile memory, one problem is that this error will need to be corrected for every read operation. However, when an error in a different position in the data signal group is identified, the single bit error correcting procedures will not be adequate and the data processing unit forced to respond to an uncorrectable error.
A need has therefore been felt for apparatus and associated method for using an error checking and correction algorithm for correcting a bit in a data signal group. It would be another feature of the apparatus and associated method to identify a failing bit as a cause of an error in the data signal group. It would be yet another feature of the apparatus and associated method to restore the charge on the failing bit in the main memory or error checking and correction memory.